On Fault Tolerance Techniques towards Nanoscale Circuits and Systems

The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shrink, it is becoming increasingly difficult to control the variance of physical parameters in the manufacturing process, for instance the concentration of dopants, the thickness of the gate and the insulation oxides, the width and thickness of metal wires, etc. This results in decreased yield which increases the costs per functioning chip. Electromigration causes intermittent and permanent failures after some period of operation, which means that these faults cannot be observed in the manufacture test. The problem of electromigration increases when going further to nanometer regime because of the decreasing width and increasing deviation of wires. Lowering the supply voltages make the circuits more vulnerable to noise and background radiation resulting in a higher soft error rate. The only reasonable way to cope with these reliability problems is to build the circuits fault tolerant. Therefore, the yield can be maintained at an acceptable level by admitting some amount of faults in a chip. Electromigration problems can be overcome by the use of built-in redundancy and dynamically reconfigurable circuit structure. The soft errors can be handled by using static redundancy methods like hardware, information and time redundancy. This report discusses fault tolerance techniques for nanoscale structures. It begins with a study of phenomena that the move towards nano introduces. A gategorization for fault types is presented and the different impacts of scaling into nano regime are connected to these types. Later in the report a number of fault tolerance techniques are examined and their suitability for nanoscale circuits and systems is evaluated. Each technique is connected to one or several fault types according to their properties for fault tolerance perspective. Finally it is concluded that no single technique is enough for tolerating all the types of faults in nanosacle circuits and systems. Therefore a combination of two or more techniques is needed. The optimal mixture is design specific according to its usage purpose and proneness to different defect sources.